Abstract: Visual information transmitted in the form of digital images is becoming a major method of communication in the modern age. But the main drawback in digital images is the inheritance of noise while their acquisition or transmission. Several noise removal algorithms have been proposed till date. One of the most powerful and perspective approaches in this area is image denoising using discrete wavelet transform (DWT). As the number of levels increased, Peak Signal to Noise Ratio (PSNR) of the image gets decreased, whereas and Mean Square Error (MSE) gets increased. The NeighShrink, BayesShrink, and VisuShrink are important methods to remove the noise from a corrupted image. These methods, however cannot recover the original image significantly since the threshold value does not minimize the noisy wavelet coefficients across scales and thus they do not give good quality of image. The adaptive denoising provides an adaptive way of setting up minimum threshold by shrinking the wavelet coefficients. This method retains the original image information efficiently by removing noise and it has the image quality parameters such as peak-to-signal noise ratio (PSNR). This thesis proposes a hardware implementation of adaptive thresholding algorithm using FPGA, which can reduce processing time considerably. The decomposition algorithm of discrete wavelet transform s designed and planned to simulate with the Hardware Description Language VHDL.

Keywords: Image denoising, discrete wavelet transform, adaptive thresholding, FPGA.